The interconnection technology of semiconductor integrated circuits to circuit bearing substrates has evolved into the use of a technique known as "flip chip" where the interconnection elements are contact bumps that are fused in a first temperature cycle to the precise locations or pads on the integrated circuit element or chip that correspond to specific locations in the corresponding circuit bearing substrate so that the contact bumps support the inverted integrated circuit in position on the substrate during a second temperature cycle where there is simultaneous fusion of all contact bumps to the corresponding circuit locations.
As the "flip chip" art has progressed, the technology has expanded from the considerations involved for individual chips in the direction of the precision necessary for interconnection of complete wafer areas to broad area circuitry. As the expansion takes place, the number of connections increases, the spacing becomes closer and any differences in interconnection height must be controlled.
Tighter constraints have further become necessary on the volume and type of metal usable in the bump, the response of that metal in the temperature cycles and the ability to perform alignment of the bump contacts to the pads on the chip in the manufacturing operation.
One technique used in the art has been to provide a carrier member for the bump metal increments wherein there is a cavity at each location of a contact bump. The cavity is filled with a metal that under a fusing temperature the surface tension of the liquid metal forms a ball shaped bump. The ball shaped bump in the carrier cavity is then brought into contact with and fused with a corresponding contact pad on the chip. The resulting structure is a ball shaped bump contact on the chip. The technology is described in U.S. Pat. No. 5,607,099.
Another technique in the art involves the use of injection molding of a liquid solder metal into measured volume, precisely located, cavities in a mold plate. The mold plate is then positioned in registration on the pad contact surface of the chip with the metal in each filled cavity in contact with the desired pad location so that a heat cycle fuses the contents of it's respective cavity to the corresponding pad on the chip. The technique is described in copending patent application Ser. No. 08/741,453 Filed Oct. 31, 1996, assigned to IBM.